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dsPIC30F
2.0
dsPIC30F DEVICE FAMILY
a wide variety of data addressing modes, together
OVERVIEW
The dsPIC30F device family employs a powerful 16-bit
architecture that seamlessly integrates the control
features of a microprocessor (MCU) with the
computational capabilities of a digital signal processor
(DSP). The resulting functionality is ideal for
applications that rely on high-speed, repetitive
computations as well as control.
The DSP engine, dual 40-bit accumulators, hardware
support for division operations, barrel shifter, 17 x 17
multiplier, a large array of 16-bit working registers and
provide the dsPIC30F CPU with extensive
mathematical processing capability. Flexible and
deterministic interrupt handling, coupled with a
powerful array of peripherals, renders the dsPIC30F
devices suitable for control applications. Reliable, field
programmable Flash program memory and data
EEPROM ensure scalability of applications that use
dsPIC30F devices.
Figure 2-1 shows a sample device block diagram
typical of the dsPIC30F product family.
FIGURE 2-1:
dsPIC30F FAMILY BLOCK DIAGRAM
X-Data Bus <16-bit>
Y-Data Bus <16-bit>
Barrel Shifter
17 x 17 Multiplier
Y AGU
Data SRAM
up to
X AGU
8 Kbytes
I/O Ports
ACCA<40>
ACCB<40>
W Register
Array
16 x 16
Program Flash and
Data EEPROM
Data Access
24
Data
EEPROM
up to
4 Kbytes
Memory
DSP Engine
Divide Control
Mapped
Program Counter
<23-bits>
23
Flash
Program
Memory
up to
Peripherals
Instruction
144 Kbytes
Legend:
MCU/DSP X-Data Path
DSP Y-Data Path
Address Path
? 2005 Microchip Technology Inc.
16-bit ALU
Prefetch & Decode
STATUS Register
24
X-Data Bus <16-bit>
DS70043F-page 5
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